The present invention relates to a semiconductor integrated circuit device including an input/output circuit and a macrocell.
With miniaturization of a semiconductor process, a problem associated with crosstalk noise has been increased in recent years. The crosstalk noise is generally known as noise produced in the other of two signal wirings via a coupling capacitance between the signal wirings when a signal level changes at one of the signal wirings where the two signal wirings are wired close to each other. A problem arises in that when the crosstalk noise occurs, operating timing gets out of order due to the fact that, for example, a transmission delay occurs in a signal transmitted through a wiring on the side subjected to the crosstalk noise, so that a semiconductor integrated circuit device is not operated properly. Contrivance has heretofore been made to a signal wiring method to avoid these problems.
A semiconductor integrated circuit device, which decides a path for a field through wiring passing through upper hierarchy of a macrocell such as a RAM by automatic selecting wiring according to a predetermined wiring algorithm, has been disclosed in, for example, a patent document 1 (Japanese Unexamined Patent Publication No. Hei 7 (1995)-37987). According to the semiconductor integrated circuit device, since the path for the field through wiring can be set freely unlike a case in which a pre-set fixed field through wiring is used, the type development of the macrocell can be facilitated.
A semiconductor integrated circuit wherein each signal line is laid with being superimposed on an area extending from one end on a circuit area, of a memory to the other end thereof, i.e., a specific area less subject to an influence due to the signal line, has been disclosed in a patent document 2 (Japanese Unexamined Patent Publication No. 2000-3963). According to the semiconductor integrated circuit, a signal is wired to an area for a decoder or the like less subject to the influence of crosstalk noise due to each signal wiring, thereby making it possible to realize a normal memory operation and improve layout efficiency.
Meanwhile, change points of a signal level, i.e., the rising and falling spots of a signal waveform are most susceptible to the crosstalk noise. Since it takes time to charge and discharge a signal wiring capacitance with changes in signal level, the rising and falling edges of the waveform become gentle. Namely, it is known that the waveform is rounded. FIG. 11 is a diagram showing an original waveform W1 and a round waveform W2 where a signal level changes from a low level to a high level. The original waveform W1 indicated by a dotted line in the same figure rises approximately vertically, whereas the rising edge of the round waveform W2 indicated by a solid line is gentle.
The rising and falling spots of the waveform are placed in a state in which the signal level is transitioned from a high level to a low level and vice versa. A transmission delay due to the influence of the crosstalk noise becomes large at both spots. When, for example, signal levels change at signal wirings adjacent to each other simultaneously, crosstalk noise is superimposed on the rising and falling spots of the waveform. FIG. 12 is a diagram showing an original waveform W1 and a round waveform W3 on which crosstalk noise is superimposed. The round waveform W3 indicated by a solid line in the same figure is disturbed in rising spot due to the overlap of the crosstalk noise (spot XT1 surrounded by a circle in the same figure). Thus, a problem arises in that a delay occurs in a transmission signal and a semiconductor integrated circuit device is not operated properly.
A signal wiring that passes over a relatively large macrocell such as a memory has a tendency that it becomes longer than other wirings. Since the signal wiring becomes long, the capacitance thereof increases normally, the rounding of a waveform also becomes large. Therefore, the relatively long signal wiring that passes over the macrocell is susceptible particularly to crosstalk noise.
Since the number of wiring layers for wiring signal wirings that pass over a macrocell is generally small, long-distance parallel wiring based on the minimum wiring pitch is normally performed where automatic wiring by an automatic wiring tool is done. In this case, an error due to crosstalk noise becomes easy to occur. Since these signal wirings are wired in parallel over a long distance at narrow intervals although an error correction subsequent to the automatic wiring is normally made manually, the correction is difficult and a long period of time is spent on correction work. When the error cannot be resolved by the wiring correction based the manual work, the layout must have been changed considerably retroactively to a layout initial step.
In the semiconductor integrated circuit device disclosed in the patent document 1, the occurrence of the transmission delay cannot be avoided where the crosstalk noise is superimposed on the rising and falling spots of the waveform, although the path for the field through wiring can be set freely. Particularly when the crosstalk noise occurs in the relatively long signal wiring that passes over the macrocell, the semiconductor integrated circuit device could not be operated properly. In the semiconductor integrated circuit disclosed in the patent document 2, the amount of crosstalk noise produced in the signal wiring per se cannot be reduced although the proper memory operation can be realized by forming the signal wiring in the area hard to be susceptible to the crosstalk noise on the circuit area of the memory. When the crosstalk noise has occurred in the relatively long signal wiring that passes over the macrocell, the whole semiconductor integrated circuit could not be operated properly.
The wiring method based on the automatic selecting wiring, which has been disclosed in the patent document 1, was accompanied by problems that the error due to the crosstalk noise was easy to occur, and waste of work and time for manual error correction work and a significant layout change retroactive to a layout initial step would occur.